The present invention relates to a liquid crystal driver circuit.
A liquid crystal driver circuit as shown in FIG. 1 is known. This liquid crystal driver circuit has a voltage divider circuit 10, a common electrode drive circuit 20 and a segment electrode drive circuit 30. The voltage divider circuit 10 has resistors R1 to R4 series-connected between power source terminals VD and VL, p-channel MOS transistors TR1 and TR2 and n-channel MOS transistors TR3 and TR4 connected in parallel with the resistors R1 to R4, and p- and n-channel MOS transistors TR5 and TR6 respectively connected in parallel with the resistors R1 to R4. Resistors R5 to R8 are respectively connected in series with the MOS transistors TR1 to TR4, and an input terminal VI for receiving a clock pulse CP is connected to the gates of the MOS transistors TR1 and TR2. The input terminal VI is connected to the gates of the MOS transistors TR3 and TR4 through an inverter 12. A control terminal CLT for receiving a voltage polarity selection signal VPS, for selecting the polarity of the voltage to be applied to the liquid crystal, is connected to the gates of the MOS transistors TR5 and TR6.
The resistors R1 to R4 have a resistance of, for example, 100 k.OMEGA., and the resistors R5 to R8 have a resistance of, for example, 10 k.OMEGA..
The common electrode drive circuit 20 has p-channel MOS transistors TR7 and TR8 and n-channel MOS transistors TR9 and TR10 whose current paths are series-connected between the power source terminals VD and VL; p- and n-channel MOS transistors TR11 and TR12 which are connected in parallel with each other between a node N1 between the resistors R2 and R3 and a node between the MOS transistors TR8 and TR9; and a NAND gate 21 which receives a first common electrode selection signal CES1 and a blanking signal BLK. The gates of the MOS transistors TR7 and TR10 are connected to the control terminal CLT through an inverter 22, the gates of the MOS transistors TR8 and TR12 are connected to the output terminal of the NAND gate 21, and the gates of the MOS transistors TR9 and TR11 are connected to the output terminal of the NAND gate 21 through an inverter 24. The node between the MOS transistors TR8 and TR9 is connected to a first common electrode bias terminal CET1. Circuit sections 25 and 26 are of the same configuration as that of a circuit section 27 indicated by the broken line in FIG. 1. The circuit sections 25 and 26 supply bias signals to second and third common electrode bias terminals CET2 and CET3 in response to output signals from NAND gates 28 and 29. One input terminal of each of the NAND gates 28 and 29 receives the blanking signal BLK, while the other input terminal thereof receives second and third common electrode selection signals CES2 and CES3.
The segment electrode drive circuit 30 has a first segment bias circuit 31-1 formed of p- and n-channel MOS transistors TR13 and TR14 which are series-connected between a node N2 between the resistors R1 and R2 and a node N3 between the resistors R3 and R4; second to N-th segment bias circuits 31-2 to 31-N of the same configuration as that of the first segment bias circuit 31-1; an N-stage register 32 for storing the segment data from an external circuit (not shown); and latch circuits 33-1 to 33-N which are coupled to the N output stages of the register 32. The segment bias circuits 31-1 to 31-N are respectively connected to segment electrode bias terminals SET1 to SETN.
The mode of operation of the liquid crystal driver circuit shown in FIG. 1 will now be described with reference to FIGS. 2A to 2G. FIGS. 2A to 2E respectively show the clock pulse supplied to the input terminal VI, the common electrode selection signals CES1 to CES3 supplied to the NAND gates 21, 28, and 29, and the signal supplied to the control terminal CLT.
The potentials at the nodes N1, N2 and N3 of the voltage divider circuit 10 are each set at one of two levels in accordance with the voltage polarity selection signal VPS applied to the control terminal CLT, as shown in Table 1 below:
TABLE 1 ______________________________________ VPS HIGH LOW ______________________________________ N1 1/3(VD - VL) 2/3(VD - VL) N2 2/3(VD - VL) VD N3 VL 1/3(VD - VL) ______________________________________
The MOS transistors TR1 to TR4 are incorporated to speed up the setting of the potential levels at the nodes N1 to N3. When the clock pulse CP is supplied to the input terminal VI, these MOS transistors TR1 to TR4 are all turned on. Therefore, the potential levels at the nodes N1 to N3 are determined quickly in accordance with the resistances of the resistors R5 to R8 and the conduction states of the MOS transistors TR5 and TR6.
In response to the voltage polarity selection signal VPS, the first to third common electrode selection signals CES1 to CES3, and the blanking signal BLK, the common electrode drive circuit 20 supplies an output signal having a selected level to the first to third common electrode bias terminals CET1 to CET3. For example, if the blanking signal BLK is at a logic level "0", the MOS transistors TR11 and TR12 and the corresponding MOS transistors in the circuit sections 25 and 26 are turned on, so that the first to third common electrode bias terminals CET1 to CET3 are set at the same potential level as that of the node N1 of the voltage divider circuit 10. As shown in FIG. 2F, these common electrode bias terminals are set at the potential level of 1/3(VD-VL) or 2/3(VD-VL) in synchronism with the voltage polarity selection signal VPS. Therefore, the liquid crystal may not be biased in this case.
On the other hand, if the blanking signal BLK is at a logic level "1", when the first common electrode selection signal CES1 is at a logic level "0", an output voltage of the potential level of 1/3(VD-VL) or 2/3(VD-VL) is supplied to the common electrode bias terminal CET1 in accordance with the potential level of the voltage polarity selection signal VPS, as shown in FIG. 2G. If the first common electrode selection signal CES1 is at a logic level "1", the MOS transistors TR8 and TR9 are turned on, and an output voltage of the same potential level as that of the voltage polarity selection signal VPS is supplied to the first common electrode bias terminal CET1. In a similar manner, voltages of VD and VL levels are applied to the second and third common electrode bias terminals CET2 and CET3 at timings different from those indicated by the waveform in FIG. 2F. In this case, in accordance with the segment data stored in the register 32, the liquid crystal is biased by a combination of the voltage supplied to the segment electrode bias terminals SET1 to SETN and the voltage supplied to the common electrode bias terminals CET1 to CET3.
When the liquid crystal driver circuit as described above is used for a CMOS one-chip microcomputer of low power consumption as shown in FIG. 3, a current flows through the resistors R1 to R4, for example, to consume power even while data is not displayed by the blanking signal BLK. If the MOS transistors TR1 to TR4 are on, a greater current such as 100 nA flows through the resistors TR1 to TR4. For this reason, the power consumption of the overall microcomputer is increased, and the low power consumption feature of the CMOS transistor circuit is impaired.